This invention relates to digital frequency synthesizers and particularly to such synthesizers which do not use phase locked loop techniques in their basic structure.
Digital frequency synthesizers are well known and their technology is well developed. Usually such synthesizers are of the phase locked loop type wherein a reference frequency source is phase locked to an output frequency signal which has been divided down by a variable digital frequency divider. The output frequencies are thus generally equal to the reference frequency times a factor N, where N is the divisor of the variable divider. The available output frequencies are thus evenly spaced by an amount equal to the reference frequency.
For frequencies which are less than the reference frequency, it is merely necessary to divide the reference frequency. If a variable digital frequency divider is used then the output frequencies obtainable are equal to the reference frequency divided by an interger N, where N is the divisor of the variable divider. Of course, in this case, the output frequencies are not evenly spaced.